This application claims the priority of Korean Patent Application No. 2003-93682, filed on Dec. 19, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a method of fabricating a transistor semiconductor device, and more particularly to a method of fabricating a recess channel array transistor.
2. Description of the Related Art
Increased integration densities and decreased design rules of integrated semiconductor devices place challenges on the stable operation of transistors. For example, a decreased design rule of an integrated circuit device results in a decrease of a gate width, so that a channel of a transistor is significantly shortened. Accordingly, a so-called short channel effect frequently occurs.
A short channel induces punchthrough between a source and a drain of a transistor. Such punchthrough is regarded as a major cause of malfunctions in the transistor device. In order to overcome the short channel effect, methods are being researched to secure longer channel lengths regardless of the design rule. In particular, considerable efforts are being made to form a recess channel array transistor in which a silicon substrate is recessed under a gate, thereby extending the channel length.
FIGS. 1 through 5 are cross-sectional views illustrating a conventional method of fabricating a recess channel array transistor.
Referring to FIG. 1, an isolation insulating layer 104 that fills a trench 102 of a silicon substrate 100 is formed to define an active region AR. The isolation insulating layer 104 is an oxide layer. The isolation insulating layer 104 is a field region FR. A liner layer 103 is formed along an inner wall of the trench 102, thereby shielding the isolation insulating layer 104. The liner layer 103 is a nitride layer.
A buffer insulating layer 106 is formed on the silicon substrate 100 and the isolation insulating layer 104. The buffer insulating layer 106 is an oxide layer having a thickness of 100 to 200 Å. Then, a polysilicon mask layer 108 is formed on the buffer insulating layer 106 to a thickness of 1000 Å.
Referring to FIG. 2, an organic anti-reflective coating layer 110 is formed on the polysilicon mask layer 108 to a thickness of 800 Å. The organic anti-reflective coating layer 110 prevents reflection of light from the polysilicon mask layer 108 during exposure for forming a photoresist pattern in a subsequent process. A photoresist pattern 112 is formed on the organic anti-reflective coating layer 110 using a photolithography process.
Referring to FIG. 3, using the photoresist pattern 112 as an etch mask, the organic anti-reflective coating layer 110, the polysilicon mask layer 108 and the buffer insulating layer 106 are etched, thereby sequentially forming an organic anti-reflective coating layer pattern 110a, a polysilicon mask layer pattern 108a and a buffer insulating layer pattern 106a. The organic anti-reflective coating layer 110, the polysilicon mask layer 108 and the buffer insulating layer 106 are plasma etched using HBr and Cl2 gas by means of polysilicon etching equipment. A surface of the silicon substrate 100 is partially exposed through the organic anti-reflective coating layer pattern 110a, the polysilicon mask layer pattern 108a and the buffer insulating layer pattern 106a. A recess channel trench is subsequently formed in the exposed portion of the silicon substrate 100 in a subsequent process.
Referring to FIG. 4, the photoresist pattern 112a and the organic anti-reflective coating layer pattern 110a used as etch masks are sequentially removed. Thus, the buffer insulating layer pattern 106a and the polysilicon mask layer pattern 108a remain on the silicon substrate 100.
Referring to FIGS. 4 and 5, the silicon substrate 100 and the isolation insulating layer 104 are plasma etched using the polysilicon mask layer pattern 108a and the buffer insulating layer pattern 106a as an etch mask, thereby forming recess channel trenches 114 and 116. The plasma etching is performed by means of polysilicon etching equipment using a gas containing Ar, CF4, Cl2 and O2.
The recess channel trenches 114 and 116 can be etched in two steps. First, the silicon substrate 100 is etched while etching the polysilicon mask layer pattern 108a. Secondly, over-etching is performed.
Because the polysilicon mask layer pattern 108a and the silicon substrate 100 have similar etch rates, the silicon substrate 100 is etched as deep as the height of the polysilicon mask layer pattern 108a, thereby determining a depth H1 of the recess channel trench 116. In other words, the depth H1 of the recess channel trench 116 depends on the height of the polysilicon mask layer pattern 108a. 
On the other hand, the etch selectivity of the polysilicon mask layer pattern 108a with respect to the isolation insulating layer 104 is high. Therefore, the depth H2 of the recess channel trench 114 formed in the isolation insulating layer 104 is shallower than a depth H1 of the recess channel trench 116 formed in the silicon substrate 100. Thereafter, a gate oxide layer (not shown) and a recess gate stack (not shown) are formed within the recess channel trenches 114 and 116, thereby completing the recess channel array transistor.
The conventional method of fabricating the recess channel array transistor including the processing step shown in FIG. 3 is disadvantageous in that the buffer insulating layer 106 cannot be effectively etched because the polysilicon mask layer 108 is etched using polysilicon layer etching equipment. That is, since the HBr and Cl2 gases used when etching the polysilicon mask layer 108 have a high etch selectivity with respect to an oxide layer, by-products generated during the etching adhere to the buffer insulating layer 106 and undesirably generate oxide etch residues when the buffer insulating layer 106 is exposed after etching the polysilicon mask layer 108. These residues deteriorate the profiles and the uniformity of the depths of the recess channel trenches.
Moreover, in the prior art, it has been difficult to adjust the depths of the recess channel trenches and to secure uniformity when etching the silicon substrate during the process of forming the recess channel trenches described with reference to FIGS. 4 and 5. To further illustrate these difficulties, the processing steps of forming the recess channel trenches formed in the silicon substrate 100 will be described with reference to FIGS. 6, 7 and 8. FIGS. 6, 7 and 8 are perspective views illustrating the processing steps for forming the recess channel trenches shown in FIGS. 4 and 5. Like reference numerals in FIGS. 6 through 8 and FIGS. 4 and 5 denote like elements.
Referring to FIG. 6, the buffer insulating layer pattern 106a and the polysilicon mask layer pattern 108a are formed on the silicon substrate 100. The silicon substrate 100 is exposed by the buffer insulating layer pattern 106a and the polysilicon mask layer pattern 108a. The exposed portion of the silicon substrate 100 will have the recess channel trench 116 formed therein. Generally, the portion where the recess channel trench 116 is formed is a narrow region NR, e.g., a cell region, of the silicon substrate 100, and the other portion where the recess channel trench is not formed is a wide region WR.
FIG. 7 shows the recess channel trench 116 partially completed. Using the polysilicon mask layer pattern 108a and the buffer insulating layer pattern 106a as an etch mask, the silicon substrate 100 is etched to form the recess channel trench 116 in the narrow region NR. As shown in FIG. 7, a depth of the recess channel trench 116 corresponds to the height of an etched portion 120 of the polysilicon mask layer pattern 108a. In FIG. 7, arrows denote an etching orientation.
FIG. 8 shows the formation of the recess channel trench 116 that is completed. Using the polysilicon mask layer pattern 108a and the buffer insulating layer pattern 106a as an etch mask, the recess channel trench 116 is formed by etching the silicon substrate 100 in the narrow region NR. The depth of the recess trench 116 corresponds to the height of an etched portion 122 of the polysilicon mask layer pattern 108a. 
However, because the recess channel trench 116 shown in FIG. 8 is formed in the narrow region (cell region) only, the ambient within an etching chamber varies if the buffer insulating layer pattern 106a of the wide region is exposed after thoroughly etching the polysilicon mask layer pattern 108a. Thus, the plasma etching gas can be concentrated on the recess channel trench 116 formed in the narrow region NR, as denoted by the arrows in FIG. 8, making it difficult to adjust the depth of the recess channel trench 116 and to secure etching uniformity of the silicon substrate 100.
Accordingly, there is a need for a method of fabricating a recess channel array transistor in which a depth of a recess channel trench can be easily controlled and good etching uniformity of a silicon substrate can be obtained.